A lead-frame-based semiconductor package using a lead frame as a chip carrier usually renders a reliability issue in terms of thermal stresses being generated due to mismatch in CTE (coefficient of thermal expansion) between a chip and a silver paste for attaching the chip to the lead frame and between the silver paste and the lead frame. In particular, the chip is mounted on a die pad of the lead frame via the silver paste and encapsulated by an encapsulant; due to different CTEs (chip: about 4 ppm, silver paste: about 40 ppm, die pad: about 16 ppm), significant thermal stresses would be induced at interfaces between the chip and silver paste and between the silver paste and die pad, such that under temperature variation in a reliability test or practical operating environment, the semiconductor package may be subject to delamination and chip cracks by effect of thermal stresses, making quality of the semiconductor package undesirably degraded. This situation is more severe in the use of a larger die pad or chip in which contact area between the die pad and chip is increased and the die pad would suffer greater thermal stresses during a temperature cycle, thereby resulting in warpage and poor planarity of the die pad and further causing delamination between the chip and die pad.
In response to the above problems, U.S. Pat. Nos. 5,233,222, 5,327,008 and 5,521,428 disclose a semiconductor package having a die pad being formed with at least an opening. As shown in FIGS. 9A and 9B, this semiconductor package 4 utilizes a die pad 400 formed with at least an opening 402 of a flexible shape such as round, rectangle, square, etc. As such, when a chip 42 is mounted on the die pad 400 via a silver paste 45, the chip 42 covers the opening 402 with its non-active surface being partly exposed to the opening 402, making area applied with the silver paste 45 between the chip 42 and die pad 400 effectively reduced; this thereby reduces thermal stress effect on the chip 42 and die pad 400 so as to prevent delamination between the same or chip cracks from occurrence. In another aspect, with provision of the opening 402, the chip 42 would be indirect contact with a molding compound (CTE: about 14 ppm) used for forming an encapsulant 44 that encapsulates the chip 42; relatively smaller CTE mismatch between the chip 42 and encapsulant 44 helps prevent delamination and thereby assures structural intactness of the semiconductor package 4 during fabrication processes.
Besides the above benefits accomplished by the semiconductor package 4, however, during a process for applying the silver paste 45 used to attach the chip 42 to the die pad 400, it is necessary to precisely control an applied amount of the silver paste 45 in order not to affect subsequent packaging processes of the chip 42. As shown in FIG. 10A, if an excess amount of silver paste 45 is used, when the chip 42 is mounted to and presses on the silver paste 45, a portion of the silver paste 45 would leaks downwardly from a periphery of the opening 402 and flashes to a bottom surface of the die pad 400, which would adversely affect bonding between the bottom surface of the die pad 400 and the encapsulant 44. On the other hand, as shown in FIG. 10B, if an insufficient amount of silver paste 45 is applied, gaps G may be formed between the chip 42 and die pad 400 and normally of a size smaller than 1 mil (about 25.4 μm). Such gaps G failed to be filled or penetrated by a resin compound whose filler size is usually larger than 1 mil during a molding process for fabricating the encapsulant 44. Moreover, these considerably small gaps G would impede flowing of the resin compound, making air trapped between the chip 42 and die pad 400 not capable of being dissipated and thus form voids, such that the encapsulant 44 may encounter popcorn effect by virtue of voids in a high temperature environment and thus damages structures of the chip 42 and semiconductor package 4. Therefore, either flashes of the silver paste 45 or formation of voids would undesirably affect yield and reliability of fabricated package products. However, in respect of precisely controlling a used amount of the silver paste 45, it requires improvement in process accuracy or preciseness and thereby increases fabrication costs, which still may not completely eliminate the occurrence of paste flashes or voids.
Moreover, the above die pad 400 formed with the opening 402 needs to be fabricated in compliance with size and shape of the chip 42, making fabrication costs undesirably increased. For a highly integrated chip of a larger size, if such a larger chip is directly attached to the die pad, this would increase contact area between the chip and die pad and thermal stress effect on the chip and die pad, making adhesion at interfaces between the chip and silver paste and between the silver paste and die pad adversely degraded.